The present invention relates to computer memory and, more specifically, to systems and methods for testing computer memory.
Typical computer memory devices include an output capture latch. This latch may be composed of several output latches. The output latch, captures the output of the memory device, typically one address at a time. An “address,” as used herein, refers to row or column in an array. Selection of a particular address causes the contents of the row or column to be output. The contents are typically output in parallel. That is, selection of an address for output causes several bits to output to and captured by the output latch. It shall be understood that the output latch may be formed of several individual latches.
Memory devices may be tested by an Array Built in Self Test (ABIST). The ABIST may be implemented, at least in part, in hardware. The ABIST sends test patterns to the memory device. The ABIST then causes the patterns to be output by the memory and compares this output to the test patterns. Typically, the determination of memory validity is, at least initially, determined on a per-address basis.
Preferably, the ABIST should not introduce many (or any) circuit elements into system paths having critical timing constraints. To this end, one approach to implementing an ABIST has been to replicate the output latch and perform the testing based on the data captured by these extra latches. Of course, such a solution increases both power consumption and required space.